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3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71V256SB
FEATURES
* Ideal for high-performance processor secondary cache * Fast access times: -- 12/15/20ns * Inputs are 2.5V and LVTTL compatible: VIH = 1.8V * Outputs are LVTTL compatible * Low standby current (maximum): -- 2mA full standby * Small packages for space-efficient layouts: -- 28-pin 300 mil SOJ -- 28-pin TSOP Type I * Produced with advanced high-performance CMOS technology * Single 3.3V(0.3V) power supply
DESCRIPTION
The IDT71V256SB is a 262,144-bit high-speed static RAM organized as 32K x 8. The improved VIH (1.8V) makes the inputs compatible with 2.5V logic levels. The IDT71V256SB is otherwise identical to the IDT71V256SA. The IDT71V256SB has outstanding low power characteristics while at the same time maintaining very high performance. Address access times of as fast as12 ns are ideal for tag SRAM in secondary cache designs. When power management logic puts the IDT71V256SB in standby mode, its very low power characteristics contribute to extended battery life. By taking CS HIGH, the SRAM will automatically go to a low power standby mode and will remain in standby as long as CS remains HIGH. Furthermore, under full standby mode (CS at CMOS level, f=0), power consumption is guaranteed to always be less than 6.6mW and typically will be much smaller. The IDT71V256SB is packaged in 28-pin 300 mil SOJ and 28-pin300 mil TSOP Type I packaging.
FUNCTIONAL BLOCK DIAGRAM
A0 ADDRESS DECODER A14 262,144 BIT MEMORY ARRAY
VCC GND
I/O0 INPUT DATA CIRCUIT I/O7
I/O CONTROL
CS OE WE
CONTROL CIRCUIT
3770 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
(c)1997 Integrated Device Technology, Inc.
JANUARY 1997
7.??
3770/1
1
IDT71V256SB 3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23
ABSOLUTE MAXIMUM RATINGS(1)
VCC
WE
Symbol VTERM
(2)
Rating Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Com'l. -0.5 to +4.6 -0.5 to VCC+0.5 0 to +70 -55 to +125 -55 to +125 1.0 50
Unit V V C C C W mA
A13 A8 A9 A11
OE
VTERM(3) TA TBIAS TSTG PT IOUT
SO28-5
22 21 20 19 18 17 16 15
A10
CS
I/O7 I/O6 I/O5 I/O4 I/O3
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SOJ TOP VIEW
OE
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
A10
CS
A11 A9 A8 A13
WE
VCC A14 A12 A7 A6 A5 A4 A3
SO28-8
I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
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NOTES: 3770 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals only. 3. Input, Output, and I/O terminals; 4.6V maximum.
CAPACITANCE
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 3dV VOUT = 3dV Max. Unit 6 7 pF pF
TSOP TOP VIEW
NOTE: 3770 tbl 04 1. This parameter is determined by device characterization, but is not production tested.
PIN DESCRIPTIONS
Name A0-A14 I/O0-I/O7
CS WE OE
Description Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power
3770 tbl 01
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Commercial Temperature 0C to +70C GND 0V VCC 3.3V 0.3V
3770 tbl 05
GND VCC
TRUTH TABLE(1)
WE CS OE
I/O High-Z High-Z High-Z DOUT DIN
Function Standby (ISB) Standby (ISB1) Output Disable Read Write
3770 tbl 02
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage - Inputs Input High Voltage - I/O Input Low Voltage Min. Typ. 3.0 0 1.8 1.8 -0.5(1) 3.3 0 -- -- -- Max. Unit 3.6 0 5.0
Vcc+0.3
X X H H L
H VHC L L L
X X H L X
V V V V V
NOTE: 1. H = VIH, L = VIL, X = Don't Care
0.8
NOTE: 3770 tbl 06 1. VIL (min.) = -1.0V for pulse width less than 5ns, once per cycle.
2
IDT71V256SB 3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 3.3V 0.3V, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) (2) CS = VIH, VCC = Max., Outputs Open, f = fMAX Full Standby Power Supply Current (CMOS Level) (2) CS VHC, VCC = Max., Outputs Open, f = 0 , VIN VLC or VIN VHC 71V256SB12 Com'l 90 20 2 71V256SB15 Com'l. 85 20 2 71V256SB20 Com'l. 85 20 2 Unit mA mA mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, only address inputs cycling at fmax; f = 0 means that no inputs are cycling.
3770 tbl 07
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V 0.3V
IDT71V256SB Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min. -- -- -- 2.4 Typ. -- -- -- -- Max. 2 2 0.4 -- Unit A A V V
3770 tbl 08
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
3770 tbl 09
3.3V 320 DATAOUT 350 30pF*
3.3V 320 DATAOUT 350 5pF*
3770 drw 04
3770 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ) *Includes scope and jig capacitances
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IDT71V256SB 3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V 0.3V, Commercial Temperature Range)
71V256SA12 Symbol Parameter Min. 12 -- -- 5 0 -- 3 2 3 12 9 9 0 9 0 6 0 4 1 Max. -- 12 12 -- 8 6 -- 6 -- -- -- -- -- -- -- -- -- -- 8 Read Cycle tRC Read Cycle Time tAA Address Access Time tACS tCLZ tOE tOLZ(1) tOHZ(1) tOH
(1)
71V256SA15 Min. 15 -- -- 5 0 -- 0 0 3 15 10 10 0 10 0 7 0 4 1 Max. -- 15 15 -- 9 7 -- 7 -- -- -- -- -- -- -- -- -- -- 9
71V256SA20 Min. 20 -- -- 5 0 -- 0 0 3 20 15 15 0 15 0 8 0 4 1 Max. -- 20 20 -- 10 8 -- 8 -- -- -- -- -- -- -- -- -- -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3770 tbl 10
Chip Select Access Time Chip Select to Output in Low-Z Chip Select to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change
tCHZ(1)
Write Cycle tWC Write Cycle Time tAW Address Valid to End-of-Write tCW Chip Select to End-of-Write tAS tWP tWR tDW tDH tOW(1) tWHZ(1) Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from Write Time Output Active from End-of-Write Write Enable to Output in High-Z
NOTE: 1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOH
tOE t OLZ
CS
(2)
t OHZ
(2)
tACS t CLZ DATAOUT
(2)
t CHZ DATA VALID
(2)
3770 drw 06
NOTES: 1. WE is HIGH for Read cycle. 2. Transition is measured 200mV from steady state.
4
IDT71V256SB 3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
3770 drw 07
tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
tACS tCLZ DATAOUT
(5)
t CHZ DATA VALID
(5)
3770 drw 08
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 5, 7) WE
t WC ADDRESS tOHZ
OE
(6)
t AW
CS
t AS
WE
tWP
(7)
t WR
t WHZ DATAOUT
(4)
(6)
tOW (6)
(4)
t DW DATAIN
t DH
DATA VALID
3770 drw 09
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified tWP. 5
IDT71V256SB 3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 4) CS
tWC ADDRESS tAW
CS
tAS
WE
tCW
(5)
t tWR
t DW DATAIN DATA VALID
t DH
3770 drw 10
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified tWP.
ORDERING INFORMATION
IDT 71V256 Device Type SB Power/ Rev XX Speed Y Package X Process/ Temperature Range Blank Y PZ 12 15 20 SB Commercial (0C to +70C) 300 mil SOJ (SO28-5) TSOP Type I (SO28-8)
Speed in nanoseconds
Standard Power, 2.5V Compatible Inputs
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